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William Salcedo

2x founder

William Salcedo

Partcl | Fast Chips & Systems

2025CEO· Partcl
Founder · since 2020
Company
Partcl
Role
CEO
current
Stage
—
no public source
Raised
—
no public source
Based
—
Founder / co-founder — the company's markEmployee / research role
Source: LinkedIn work history
Profile coverage5 of 7 · missing posts, contact
Partcl logo
Partcl

Design a chip in minutes

Spring 2025

Experience

Career

  • Partcl logo

    Partcl

    CEO · 2025 – Present

    2025
  • Stanford University logo

    Stanford University

    Research Assistant · 2023 – 2024

    2023
  • Stanford University logo

    Stanford University

    Course Assistant · Stanford, CA · 2024

    2024
  • NVIDIA logo

    NVIDIA

    SM ASIC Performance · Santa Clara, California, United States · 2024

    2024
  • Efabless Corporation logo

    Efabless Corporation

    Consultant · 2024

    2024
  • Cornell Custom Silicon Systems logo

    Cornell Custom Silicon Systems

    Founder

    Digital Subteam Lead · Ithaca, NY · 2022 – 2023

    2022
  • Aabix Corporation logo

    Aabix Corporation

    Founder

    Founder - Chief Product Officer · Ithaca, New York, United States · 2020 – 2023

    2020
  • Cornell Engineering logo

    Cornell Engineering

    Graduate Student Researcher · Ithaca, NY · 2023

    2023
  • Amazon logo

    Amazon

    Hardware Development Engineering Intern · Seattle, WA · 2022

    2022
  • Cornell Autonomous Sailboat Team (CUSail) logo

    Cornell Autonomous Sailboat Team (CUSail)

    Team Lead · Ithaca, New York, United States · 2021 – 2022

    2021
  • Cornell Autonomous Sailboat Team (CUSail) logo

    Cornell Autonomous Sailboat Team (CUSail)

    Navigation Team Member · Ithaca, New York Area · 2019 – 2021

    2019
  • PSEG logo

    PSEG

    Nuclear Engineering Intern · Salem, NJ · 2021

    2021

Bio

CEO at Partcl. Previously at Nvidia, Stanford, and Cornell. I taped-out two chips from scratch as an undergrad and developed one of the earliest chips designed by LLMs. My research at Stanford included using AI techniques to verify circuits.